NIST: Single-Electron Tunneling, Gaithersburg

Quantum Processes and Metrology Group

Single Electron Tunneling at NIST, Gaithersburg

Figure 1a. Lateral view of single-crystal Si wire (running horizontally) covered by thin thermal gate oxide and then three poly-Si "finger gates" running vertically.

Figure 1b. Magnification 150,000 X

Figure 1b. Cross-sectional view along purple line in Figure 1a, showing crystalline Si (central rectangle) surrounded by gate oxide, lower finger gate and then the large upper gate (not shown in 1a).

Research into the use of SET devices goes on at both NIST Gaithersburg (led by Neil M. Zimmerman) and NIST Boulder (led by Mark W. Keller). This page describes the research at NIST Gaithersburg.

Project Summary:

We are working on using SET devices as a possible realization of quantum coherence. Efforts include:

Achieving a reliable fabrication process for electrostatically-gated Si-based SET transistors (see Figure 1). We are trying to develop a process that yields good uniformity of devices, and also provides high resistance to the problem of charge offset drift.

Investigating quantum coherence based on the charge state of two coupled quantum dots. For this effort, we are present (as of July 2007) investigating both developing a RF-SETT using Si-based transistors, and also investigating various architectures for developing a charge qubit in a Si device.

Publications:

Figure 2. Cross-sectional view of three-dimensional single-electron tunneling transistor, fabricated from an Al/AlO_x/Al trilayer using focused ion beam etching.